The present invention relates to very large scale integrated circuits, and to methods for fabrication thereof.
Interconnect technology is increasingly a major limitation in the fabrication of very large scale integrated circuits. In particular, the use of multiple patterned polysilicon or metal layers for interconnects places great pressure on the processing technology related to etching of contact holes and planarization of interlevel dielectrics. However, the additional routing capability which is provided by any additional level of interconnect will often give circuit designers options which translate into more compact layouts, better circuit performance, and/or greater ease of circuit design.
For these reasons much effort has been dedicated to modifying processes to include a buried contact. A buried contact process is a process which uses a single layer to form not only MOS gates, but also, using other patterned portions of the same layer, contact to the source/drain regions of MOS transistors. That is, the same thin film polysilicon or polycide layer must in some locations be separated from the moat by a very thin high-integrity gate oxide, and in other locations must form an ohmic contact to highly doped moat regions. This leads to three main classes of processing problems: first, gate oxide integrity becomes more difficult to preserve. Second, scalability is limited by interdiffusion between the polysilicon material and the bulk silicon. That is, the phosphorus doping used to make the polysilicon conductive will normally outdiffuse into the silicon substrate at the contact location. However, as devices are scaled to small geometries, this phosphorus diffusion can counterdope a major fraction of the channel stop doping, leading to leakage between active areas. Third, first contacts are highly desirable in CMOS processing, but present technology does not provide any manufacturable process to make contact to P+ moat regions. Not only is there the problem of how to avoid a diode between N+ poly and P+ substrate, but similar problems of dopant outdiffusion may lead to shorting from the poly to the PMOS substrate at first contacts to P+.
There have been published suggestions of ways to provide a local interconnect level in the context of a self-aligned titanium silicide process for source/drain silicidation. The self-aligned titanium silicide source/drain silicidation process is disclosed in U.S. patent application Ser. No. 492,069, filed May 6, 1983, (TI-9596), now U.S. Pat. No. 4,545,116, which is hereby incorporated by reference. In this process, metallic titanium is deposited overall, and is then heated in a nitrogen atmosphere so that the titanium reacts with exposed silicon surfaces (such as source/drain regions, or exposed upper surfaces of polysilicon lines) to form titanium silicide. The portions of titanium which did not react to form silicides are then stripped (using, for example, a wet etch). This process provides a self-aligned silicidation process without any patterning steps. This self-aligned silicidation process has come into wide use in integrated circuit fabrication.
The previously proposed local interconnect schemes based on this process use additional patterned silicon to provide conductive silicide regions extending out over the field oxide as desired. That is, in the process developed by Hewlett Packard and published at Page 118 of the 1984 IEDM Proceedings, (which publication is hereby incorporated by reference), after the titanium metal is deposited overall, and before heat is applied to effect silicide reaction, a thin layer of silicon (either polycrystalline or amorphous) is patterned on top of the titanium metal. Where this silicon layer has been applied, a silicide will form during the reaction process, so that silicides can be formed extending over the gate sidewall oxide or over the field oxide. A similar approach previously developed at Texas Instruments used patterned silicon straps which were applied before the titanium metal was applied.
However, both of these approaches have the limitation that deposition of an additional layer is required. Thus, both of these approaches contain excess processing complexities.
Other publications relevent to examination of the present application may be found in the paper by C. Y. Ting at page 110 of the 1984 IEDM proceedings (and see especially page 113) and in the paper by M. Alperin et al., Development of the Self-aligned TiSi.sub.2 Process for VLSI applications, at page 141 of the February 1985 issue of the IEEE transactions on Electron Devices.
The present invention provides a simpler method of forming local interconnects in the context of a self-aligned direct-react titanium silicide process for source/drain (and preferably gate) silicidation.
It has been discovered that when the direct-react titanium silicide silicidation process is performed in a nitrogen atmosphere, a surface layer of titanium nitride (TiN) is formed in the titanium metal layer over field oxide. Thus, after the silicide reaction occurs, the portions of the deposited titanium metal layer which have not been in contact with a source of silicon (and therefore have not formed silicide) are not merely unreacted titanium metal, but include a large fraction of titanium nitride. The present invention makes use of this titanium nitride layer to provide a new and advantageous local interconnect method and structure.
After the silicidation step, the titanium nitride layer is patterned and selectively removed from titanium silicide and silicon oxide regions where it is not desired. After this, a final anneal is performed at higher temperature (e.g. 800 C) to reduce the final sheet resistance of the titanium silicide layers to below one ohm per square.
This provides a structure wherein moat-to-moat interconnections have been formed using a very thin (e.g. 1000 angstroms) layer of titanium nitride. Not only is the processing simpler than the methods for forming titanium silicide local interconnects discussed above, but also the present invention provides further advantages as well. First, titanium nitride is a very good diffusion barrier, so problems of interdiffusion through the silicide are avoided. This is particularly advantageous where the local interconnect layer is used to connect a p+ moat region to an n+ moat region in CMOS processing. Second, as noted, the titanium nitride layer is extremely thin, so that the amount of additional vertical topography induced in subsequent unplanarized layers is minimal. Third, since the titanium nitride layer is so thin, the etch used to remove it need not be anisotropic, which again simplifies processing. Fourth, even a very thin titanium nitride layer can provide very low sheet resistances, of the order of one to five ohms per square, or even less. Fifth, this titanium nitride layer provides a diffusion barrier in place for contacts. That is, contacts to moat can deposit metal on top of the titanium nitride layer rather than directly on silicon, so that interdiffusion between metal and silicon is effectively prevented. This simplifies the selection of interconnect metallization. Sixth, the overlap of the titanium nitride onto the field oxide means that the contact holes need not be perfectly aligned to the edge of the moat, but the contact hole can overlap onto the titanium nitride over the upper surface of the edge of the field oxide. Seventh, the capability of the present invention will permit the elimination of double-level metal (DLM) process steps in some processes, without any sacrifice of speed or area, since this provides a lower interconnect layer of such good conductivity that strapping is not necessary. Eighth, the number of second contacts in a layout can be reduced, since independent interconnection through the TiN layer can substitute for some metal interconnects. Ninth, the present process is inherently amenable to shared contacts, i.e. to contacts where contact is made between two interconnect layers and substrate at the same location. Tenth, the methods using silicon straps for local interconnect are inherently susceptible to open circuit defects where the silicon strap crosses the angle at the foot of the gate, and, to avoid this, the silicon straps need to be made relatively thick (as much as 2500 A thick in some processes), which degrades topography and throughput. By contrast, the TiN straps of the present invention do not have this problem, and therefore do not need to be made so thick. Eleventh, titanium nitride is more resistant to oxide etches than titanium silicide is, so that damage caused by overetching the multilevel oxide at the contact etch step in a process using a planarized multilevel oxide are reduced. Twelfth, the capability of overlapping moat contacts up onto the field oxide means that minimum geometry can be used for the source/drain regions in the moat. Thirteenth, the present invention permits connection between stages of CMOS logic to be accomplished without any contact holes, which provides advantages in area, speed, and yield.
It is well-known in the integrated circuit art that titanium nitride is conductive, and the use of titanium nitride as a conductive diffusion barrier in contacts has been previously published; but no published work is known to discuss the use of titanium nitride to provide local interconnects, as in the present invention.
According to the present invention there is provided: An integrated circuit comprising:
a silicon substrate; PA0 device isolation regions defining predetermined moat areas; PA0 a plurality of active devices in said moat areas; PA0 titanium nitride local interconnect layer comprising lines of titanium nitride interconnecting predetermined portions of said moat regions over said device isolation regions. PA0 providing a substrate; PA0 providing device isolation areas in a predetermined pattern to define predetermined moat regions; PA0 fabricating insulated gate field effect transistors in predetermined locations in said moat regions; PA0 depositing titanium metal over all; PA0 heating said substrate and said titanium metal in a nitrogen-bearing atmosphere, so that said titanium metal reacts with exposed silicon portions of said substrate to form titanium silicides, and other portions of said titanium metal also react with said nitrogen atmosphere to form titanium nitride; and PA0 patterning said titanium nitride layer to provide local interconnection in a predetermined pattern.
According to the present invention there is also provided: A method for fabricating integrated circuits, comprising the steps of: